Pour les employeurs
Ingénieur Vérification ASIC (H/F)
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il y a 12 jours
Date de publication
il y a 12 jours
S/O
Niveau d'expérience
S/O
Temps pleinType de contrat
Temps plein
AutreCatégorie d'emploi
Autre
Eviden is an Atos Group business with an annual revenue of circa € 5 billion and a global leader in data-driven, trusted and sustainable digital transformation. As a next generation digital business with worldwide leading positions in digital, cloud, data, advanced computing and security, it brings deep expertise for all industries in more than 47 countries. By uniting unique high-end technologies across the full digital continuum with 55,000 world-class talents, Eviden expands the possibilities of data and technology, now and for generations to come.

Mission description:

As part of the development of ASICs such as network controllers, routers, cache coherence controllers and processors for high-end, high-performance Bull servers ("big data" and "exascale" servers), the mission consists of participating to verify a complex ASIC using the "Constraint-Random, Coverage Driven" functional verification methodologies underlying the UVM verification standard.

Main tasks:

• Acquire knowledge of ASIC architecture and microarchitecture by studying specifications and interacting with the architecture and logic design teams.

• Writing verification specifications. • Writing test plans in close collaboration with the logic design team. • Development of verification environments (UVM-SystemVerilog/C++), tests and coverage models • Track, analyze and debug simulation errors. • Monitor and analyze the coverage results of the simulations to improve the tests accordingly and thus achieve the coverage objectives within the set deadlines. SKILLS:

• Concrete and successful experience verifying complex SoC/ASIC and IP.

• Experience with UVM verification methodology.

• Experience in developing Constraint-Random/Coverage-Driven verification environments in SystemVerilog/C++ (drivers/monitors, constrained random tests, self-verifying checkers and coverage model in SystemVerilog-Covergrourp/SVA) and mastery of oriented programming object

• Knowledge of simulation and coverage monitoring tools

• Efficiency in resolving problems by quickly identifying their root cause and developing fixes or workarounds.

Let's grow together.
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RÉSUMÉ DE L' OFFRE
Ingénieur Vérification ASIC (H/F)
Les Clayes-sous-Bois
il y a 12 jours
S/O
Temps plein